Since the introduction of semiconductor devices, the size of semiconductor devices has been continuously shrinking, resulting in smaller semiconductor chip size and increased device density. One of the limiting factors in the continuing evolution toward smaller device size and higher density has been the stringent requirements placed on photolithographic processes as line width and step heights have decreased for device features. As one way to overcome such limitations, various methods have been implemented to increase the resolution performance of photoresists and to eliminate interfering effects occurring in the semiconductor wafer manufacturing process.
In the fabrication of semiconductor devices multiple layers may be required for providing a multi-layered interconnect structure. <During the manufacture of integrated circuits it is common to place material photoresist on top of a semiconductor wafer in desired patterns and to etch away or otherwise remove surrounding material not covered by the resist pattern in order to produce metal interconnect lines or other desired features. During the formation of semiconductor devices it is often required that the conductive layers be interconnected through holes in an insulating layer. Such holes are commonly referred to as vias, i.e., when the hole extends through an insulating layer between two conductive areas. Metal interconnecting lines (trench lines) are typically formed over the vias to electrically interconnect the various semiconductor devices within and between multiple layers. The damascene process is a well known semiconductor fabrication method for forming electrical interconnects between layers by forming vias and trench lines.
For example, in an exemplary process for forming dual damascene structures, a via opening is first etched in an insulating layer also known as an inter-metal or inter-level dielectric (IMD/ILD) layer. The insulating layer is typically formed over a metal or conductive layer. After a series of photolithographic steps defining via openings and trench openings, the via openings and the trench openings are filled with a metal (e.g., Al, Cu) to form vias and trench lines, respectively. The excess metal above the trench level is then removed by well known chemical-mechanical polishing (CMP) processes.
After the via holes are etched, but before the holes are filled with a conductive material, for example, copper, the photoresist mask which remains on top of the desired features may be removed by a dry etching method known as a reactive ion etch (RIE) or ashing process using a plasma formed of O2 or a combination of CF, and O2 to react with the photoresist material.
As feature sizes in etching process have become increasingly smaller, photolithographic processes have been required to use photoresist activating light (radiation) of smaller wavelength. Typically a deep ultraviolet (DUV) activating light source with wavelength less than about 250, for example, from about 193 nm to about 248 nm is used. Exemplary DUV photoresists, for example, include PMMA and polybutene sulfone.
One problem affecting DUV photoresist processes has been the interference of residual nitrogen-containing species with the DUV photoresist. Residual nitrogen-containing contamination is one of the greater concerns in the use or application of metal nitride films such as silicon nitride or silicon oxynitride as hard mask layer or silicon oxynitride as a DARC. The problem is exacerbated by the increasing use of low-k dielectric materials typically having a high degree of porosity, thus facilitating absorption and transport of contaminating chemical species. For example, it is believed that nitrogen radicals created due to the presence of nitrogen containing species, such as amines, interfere with chemically amplified photoresists, for example DUV photoresists by neutralizing the acid catalyst, thereby rendering that portion of the photoresist insoluble in the developer. As a result, residual photoresist may remain on patterned feature edges, sidewalls, or floors of features, affecting subsequent etching or metal filling processes leading to, for example, electrical open circuits or increased resistivity.
In a via-first dual damascene process, a method is disclosed for forming a via plug at least partially filling the via opening in commonly assigned co-pending application 2001-0155, Ser. No. 10/035,690, filed Nov. 8, 2001, which is incorporated herein by reference. For example, following formation of a via opening, a via plug of polymeric material, for example, photoresist is optionally formed to at least partially fill the via opening to protect via sidewalls in subsequent anisotropic etching processes to form a trench opening overlying and encompassing one or more via openings. Typically, a DUV photoresist is used to photolithographically pattern trench openings for anisotropic etching overlying the via openings. Frequently, the DUV photoresist layer used for patterning the trench openings, forms an undeveloped photoresist layer along a portion of the sidewalls above the via plug of the via opening believed to be caused to either contaminating chemical interference with the DUV photoresist development process or the inability of the photolithographic irradiation step to adequately expose the sidewalls of the via opening. As a result, the upper portions of the via sidewalls above the via plug are contaminated with an undeveloped photoresist layer, also referred to as photoresist poisoning, that subsequently resists plasma etching during anisotropically etching the trench portion of the dual damascene structure forming a raised portion surrounding the via opening, also referred to as a fence, following trench etching. Consequently, subsequent metal filling processes for filling the dual damascene structure with, for example copper, results in poor step coverage including where the polymeric raised portion acts as a high electrical resistance barrier area leading to electrical reliability problems of semiconductor devices including the formation of open circuits.
There is therefore a need in the semiconductor processing art to develop a method whereby reliable photolithographic processes for damascene formation may be carried out without the detrimental effects of photoresist poisoning.
It is therefore an object of the invention to provide a method whereby reliable photolithographic processes for damascene formation may be carried out without the detrimental effects of photoresist poisoning while overcoming other shortcomings and deficiencies in the prior art.